The LPC interface is a new interface specification that replaces the traditional ISA Bus on September 29, 1997, and is authorized by free open authorization for the industry. It, in order to connect the ISA expansion slot, adapter, ROM BIOS chip, Super I/O and other interfaces, the South Bridge chip must retain an ISA Bus and connect the Super I/O chip to control the traditional peripheral devices. The traditional ISA Bus rate is about 7.159 ~ 8.33MHz, and the theoretical peak transmission value is 16MB/s, but the electrical characteristics and signal definition methods of ISA Bus are very different from the traditional PCI bus. Waste the needle to do it, and the line design of the motherboard is also complicated. The LPC interface defined by Intel, separate the decoding of the address/data of the previous ISA bus to the decoding method shared by the address/data signal line similar to PCI. Synchronous driving, although the improved LPC interface maintains a maximum transmission value of 16MB/s, the number of signal foot positions required is greatly reduced by 25 to 30. The benefits of decreased foot positions and small volume, the design of the motherboard can also be simplified, which is the reason for the name LPC -LOW PIN COUNT
The LPC interface is a new interface specification that replaces the traditional ISA Bus on September 29, 1997, and is authorized by free open authorization for the industry.
It, in order to connect the ISA expansion slot, adapter, ROM BIOS chip, Super I/O and other interfaces, the South Bridge chip must retain an ISA Bus and connect the Super I/O chip to control the traditional peripheral devices. The traditional ISA Bus rate is about 7.159 ~ 8.33MHz, and the theoretical peak transmission value is 16MB/s, but the electrical characteristics and signal definition methods of ISA Bus are very different from the traditional PCI bus. Waste the needle to do it, and the line design of the motherboard is also complicated.
The LPC interface defined by Intel, separate the decoding of the address/data of the previous ISA bus to the decoding method shared by the address/data signal line similar to PCI. Synchronous driving, although the improved LPC interface maintains a maximum transmission value of 16MB/s, the number of signal foot positions required is greatly reduced by 25 to 30. The benefits of decreased foot positions and small volume, the design of the motherboard can also be simplified, which is the reason for the name LPC -LOW PIN COUNT
Which aspect of LPC do you use, LPC has many meanings.